Modern integrated circuits include a very large amount of logic circuits such as flip flops, logic gates and the like. The design process is relatively long and includes multiple stages such as high level description, synthesis, placement and routing, extraction, static timing analysis and the like.
Various vendors provide software tools capable of performing static timing analysis. These tools include, for example, Quartus® II of Altera™, of California U.S.A.; Timer™ of Actel™ of California, U.S.A., and PathMill® and PrimeTime™ of Synopsys™ of California, U.S.A.
Various verification and re-design stages are required before the design process is completed. Typically, the synthesis is responsive to design constraints (including timing constraints) and to the characteristics of designed components. The characteristics of multiple designed components are usually gathered in a cell library. Various vendors offer standard cell libraries, including Libra-Visa of Synopsys.
The following U.S. patent applications, all being incorporated herein by reference, illustrate various prior art cell libraries: U.S. patent application publication number 20050006670 of Zounes, U.S. Patent application publication number 20040237059 of Chen et al., U.S. patent application publication number 20040218831 of Liu, U.S. patent application publication number 20040195690 of Flohr, U.S. patent application publication number 20040143797 of Nguyen et al., U.S. patent application publication number 20040040004 of Sakiyama et al., and U.S. patent application publication number 20030149953 of Whitaker et al.
In general, it is harder to correct design errors during later stages of the design process, and especially after the placement and routing stages.
Static timing analysis usually includes analyzing, debugging and validating the timing performance of a design of an integrated circuit. During this stage the timing associated with the propagation of signals through a designed integrated circuit are calculated. Especially, this analysis checks whether the delay of a component fits the clock frequency requirements, and whether hold and setup violations occurred.
U.S. Pat. No. 6,591,407 of Kaufman et al., U.S. Pat. No. 5,768,159 of Belkadi et al., U.S. Pat. No. 6,237,127 of Craven et al., U.S. patent application publication number 2001/007144 of Terazawa, and PCT patent application publication number WO0075815 titled “An arrangement and a method relating to design of circuits”, all being incorporated herein by reference, provide an overview of static timing analysis.
A hold violation is determined by checking if a data or a control input signal that is provided to a certain component was steady for at least a predefined period (referred to as a worst case hold time) relative to a corresponding clock event occurred. A clock event is usually a rising or falling edge of the clock signal.
A setup violation is determined by checking if a data or a control input signal that is provided to a certain component was steady for at least a predefined period (referred to setup period) before a corresponding clock event occurred.
The worst case hold time guarantees that regardless of the setup time the component will operate in a proper manner.
There is a need to provide an effective method for static timing analysis.